Address buffer having (N/2) stages

ABSTRACT

An address buffer only having (N/2) stages, capable of performing the same function as that of an N-stage address buffer is provided. The address buffer used in a semiconductor device having N (where N is a natural number) additive latency comprises (N/2) serially-connected flip-flops, and an address control circuit which generates an address enable signal in response to a clock signal and a command signal. Each of the (N/2) flip-flops is clocked to the address enable signal and sequentially latches an external address.

BACKGROUND OF THE INVENTION

[0001] This application claims the priority of Korean Patent ApplicationNo. 2003-9808, filed on Feb. 17, 2003, in the Korean IntellectualProperty Office, the disclosure of which is incorporated herein in itsentirety by reference.

[0002] 1. Field of the Invention

[0003] The present invention relates to an address buffer used in asemiconductor device, and more particularly, to an address buffer onlyhaving (N/2) stages for processing N additive latency.

[0004] 2. Description of the Related Art

[0005] In order to increase a bandwidth, high speed semiconductor memorydevice use a scheme for artificially delaying data during a data writeoperation or a data read operation. This structure is referred to asadditive latency.

[0006]FIG. 1 is a timing diagram for explaining the concept of anadditive latency. FIG. 2 is a circuit diagram of a conventional addressbuffer used in semiconductor devices having N additive latency.Referring to FIG. 2, N flip-flops 210_1, 210_2, . . . , and 210_n areconnected serial to one another, and each of the flip-flops 210_1,210_2, . . . , and 210_n sequentially latches an external address ADD inresponse to a clock signal CLK.

[0007] Referring to FIGS. 1 and 2, when a posted CAS read (PCR) commandis input, reading of actual data in a high speed semiconductor memorydevice using additive latency is performed after additive latency (AL=2)and column address strobe (CAS) latency (CL=3). In this case, an addressis delayed by total latency (RL=5) and output.

[0008] Thus, when there is N additive latency in a semiconductor device,an address buffer including N-stage flip-flops shown in FIG. 2 isneeded. Each of the flip-flop 210_1, 210_2, and 210_n stores an addressof a PCR command that is consecutively input.

[0009] However, an interval DAL (delay address latency) between PCRcommands of a general specification is over 2 clock cycle (2CK). Thus,there is no case where an address is stored in all stages of an addressbuffer 200. That is, when the maximum address is stored in the addressbuffer 200, only (N/2) stages are needed, and thus, the other N/2 stagesare not needed.

[0010] However, when stages of the address buffer shown in FIG. 2 arereduced to (N/2), N additive latency cannot be secured. Thus, a circuitdoes not operate normally.

SUMMARY OF THE INVENTION

[0011] The present invention provides an address buffer only having(N/2) stages, capable of performing the same function as that of anN-stage address buffer.

[0012] According to one aspect of the present invention, there isprovided an address buffer used in a semiconductor device having N(where N is a natural number) additive latency. The address bufferincludes (N/2) serially-connected flip-flops, and an address controlcircuit which generates an address enable signal in response to a clocksignal and a command signal. Each of the (N/2) flip-flops is clocked tothe address enable signal and sequentially latches an external address.

[0013] The address control circuit includes an N-bit counter whichresponds to the clock signal, an AND gate which receives output signalsof the N-bit counter and performs an AND operation on the output signalsof the N-bit counter, and an OR gate which receives the command signaland an output signal of the AND gate, performs an OR operation on thecommand signal and the output signal of the AND gate, and outputs theaddress enable signal as an OR operation result.

[0014] According to another aspect of the present invention, there isprovided an address buffer used in a semiconductor device having Nadditive latency. The address buffer includes an N-bit counter whichresponds a clock signal, an AND gate which receives output signals ofthe N-bit counter and performs an AND operation on the output signals ofthe N-bit counter, an OR gate which receives the command signal and anoutput signal of the AND gate and performs an OR operation on thecommand signal and the output signal of the AND gate, and (N/2)serially-connected flip-flops. Each of the (N/2) flip-flops is clockedto the output signal of the AND gate and latches and outputs an externaladdress.

[0015] The N-bit counter is reset in response to the command signal, andthe command signal is activated in response to a data write command or adata read command.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other aspects and advantages of the presentinvention will become more apparent by describing in detail a preferredembodiment thereof with reference to the attached drawings in which:

[0017]FIG. 1 is a timing diagram for explaining the concept of anadditive latency;

[0018]FIG. 2 is a circuit diagram of a conventional address buffer usedin semiconductor devices having N additive latency;

[0019]FIG. 3 is a block diagram of an address buffer used in asemiconductor device having N additive latency according to anembodiment of the present invention; and

[0020]FIG. 4 is a timing diagram of an address control circuit shown inFIG. 3.

DETAILED DESCRIPTION OF THE INVENTION

[0021] The present invention will be described more fully hereinafterwith reference to the accompanying drawings in which a preferredembodiment of the invention are shown.

[0022] Hereinafter, the present invention will be described in detail bydescribing preferred embodiments of the invention with reference to theaccompanying drawings. Like reference numerals refer to like elementsthroughout the drawings.

[0023]FIG. 3 is a block diagram of an address buffer used in asemiconductor device having N additive latency according to anembodiment of the present invention. Referring to FIG. 3, an addressbuffer 300 used in a semiconductor device having N additive latencyincludes an address control circuit 310 and a shifting circuit 320.

[0024] The address control circuit 310 includes an N-bit counter 311, anAND gate 313, and an OR gate 315. The N-bit counter 311 is clocked to aclock signal CLK and outputs N-bit count values CNT1, CNT2, . . . , andCNTn to the AND gate 313. The N-bit counter 311 is reset in response toa falling edge of a command signal CM_EN. Here, the command signal CM_ENis activated when a write command or a read command is input.

[0025] The AND gate 313 receives output signals CNT1, CNT2, . . . , andCNTn of the N-bit counter 311, performs an AND operation on the outputsignals CNT1, CNT2, . . . , and CNTn, and outputs an AND operationresult to the OR gate 315.

[0026] The OR gate 315 receives the command signal CM_EN and an outputsignal of the AND gate 313, performs an OR operation on the commandsignal CM_EN and the output signal of the AND gate 313, and outputs anOR operation result ADD_EN as an address enable signal to the shiftingcircuit 320.

[0027] The shifting circuit 320 includes a plurality ofserially-connected flip-flops 321, 323, . . . , and 325. The flip-flop321 of a first stage latches an address ADD in response to the addressenable signal ADD_EN, and the flip-flop 323 of a second stage latches anoutput signal of the flip-flop 321 in response to the address enablesignal ADD_EN.

[0028] The flip-flop 325 of a (N/2)-th stage outputs an output signal ofa flip-flop (not shown) of a ((N/2)-1)-th stage as a buffered addresssignal BF_ADD in response to the address enable signal ADD_EN.

[0029] That is, each of serially-connected (N/2) flip-flops 321, 323, .. . , and 325 sequentially shifts an externally-input address ADDwhenever the address enable signal ADD_EN is activated. Here, eachflip-flop is also called a stage.

[0030]FIG. 4 is a timing diagram of an address control circuit shown inFIG. 3. FIG. 4 shows the case where additive latency is 2, N=2. However,the address buffer according to the present invention is not limited tothe case where additive latency is 2.

[0031] Referring to FIGS. 3 and 4, in CMD & ADD, WR_A denotes a writecommand WR and an address A, and WR_B denotes a write command WR and anaddress B, and W_C denotes a write command WR and an address C.

[0032] The case where the N-bit counter 311 is a 2-bit counter and threewrite commands WR_A, WR_B, and WR_C are consecutively input will bedescribed as below.

[0033] The 2-bit counter 311 is reset and operates in response to WR_A.Thus, when an output signal of the 2-bit counter 311 is 11, the outputsignal ADD_EN of the OR gate 315 is activated. Thus, the flip-flop 321of the first stage latches the external address ADD in response to theactivated address enable signal ADD_EN.

[0034] When the command signal CM_EN is deactivated (for example, logiclow) and the output signal of the 2-bit counter 311 is 10, the outputsignal of the AND gate 313 is deactivated. Thus, the output signalADD_EN of the OR gate 315 is deactivated.

[0035] An operation which corresponds when WR_B is input issubstantially the same as an operation which corresponds when WR_A isinput, and thus, detailed descriptions thereof will be omitted.

[0036] When WR_C is input, the 2-bit counter 311 outputs counter valuesCNT1 and CNT2 in response to a falling edge of the clock signal CLK. TheOR gate 315 outputs the address enable signal ADD_EN generated by acombination of the command signal CM_EN and the output signal of the ANDgate 313, to each of the flip-flops 321, 323, . . . , and 325. That is,the AND gate 313 and the OR gate 315 receive the output signals CNT1,CNT2, . . . , and CNTn of the counter 311, decode them, and activate theaddress enable signal ADD_EN at a point-in-time when an effectiveaddress is input.

[0037] Thus, the address enable signal ADD_EN is activated only at thepoint-in-time when the effective address is input. Thus, the number offlip-flops used in the shifting circuit 320 can be reduced. Thus, thearea of layout of the address buffer is reduced.

[0038] As described above, the address buffer used in a semiconductordevice having N additive latency according to the present invention canperform the same function as that of an N-stage address buffer byproviding only (N/2) stages. That is, an N-stage buffer can be reducedto an (N/2)-stage buffer.

[0039] While this invention has been particularly shown and describedwith reference to preferred embodiments thereof, it will be understoodby those skilled in the art that various changes in form and details maybe made therein without departing from the spirit and scope of theinvention as defined by the appended claims.

What is claimed is:
 1. An address buffer used in a semiconductor device having N additive latency, where N is a natural number, the address buffer comprising: (N/2) serially-connected flip-flops; and an address control circuit which generates an address enable signal in response to a clock signal and a command signal; wherein each of the (N/2) flip-flops is clocked to the address enable signal and sequentially latches an external address.
 2. The address buffer of claim 1, wherein the address control circuit comprises: an N-bit counter which responds to the clock signal; an AND gate which receives output signals of the N-bit counter and performs an AND operation on the output signals of the N-bit counter; and an OR gate which receives the command signal and an output signal of the AND gate, performs an OR operation on the command signal and the output signal of the AND gate, and outputs the address enable signal as an OR operation result.
 3. The address buffer of claim 2, wherein the N-bit counter is reset in response to the command signal.
 4. The address buffer of claim 1, wherein the command signal is activated in response to a data write command or a data read command.
 5. An address buffer used in a semiconductor device having N additive latency, the address buffer comprising: an N-bit counter which responds a clock signal; an AND gate which receives output signals of the N-bit counter and performs an AND operation on the output signals of the N-bit counter; an OR gate which receives the command signal and an output signal of the AND gate and performs an OR operation on the command signal and the output signal of the AND gate; and (N/2) serially-connected flip-flops; wherein each of the (N/2) flip-flops is clocked to the output signal of the AND gate and latches and outputs an external address.
 6. The address buffer of claim 5, wherein the N-bit counter is reset in response to the command signal.
 7. The address buffer of claim 5, wherein the command signal is activated in response to a data write command or a data read command.
 8. An address buffer used in a semiconductor device having N additive latency where N is a natural number, the address buffer comprising: a shifting circuit including N/2 flip-flops; an address control circuit which generates an address enable signal in response to a clock signal and a command signal; wherein each of the (N/2) flip-flops is clocked to the address enable signal and sequentially latches an external address.
 9. The address buffer of claim 8, wherein the address control circuit comprises: an N-bit counter which responds to the clock signal; an AND gate which receives output signals of the N-bit counter and performs an AND operation on the output signals of the N-bit counter; and an OR gate which receives the command signal and an output signal of the AND gate, performs an OR operation on the command signal and the output signal of the AND gate, and outputs the address enable signal as an OR operation result.
 10. The address buffer of claim 8, wherein the N-bit counter is reset in response to the command signal.
 11. The address buffer of claim 8, wherein the command signal is activated in response to a data write command or a data read command. 